#setIoFlowFlag 1
##floorPlan -site sc9mc_40ulpeflash -s 1000.02 1000.02 20.02 20.02 20.02 20.02 -adjustToSite
##floorPlan -site sc9mc_40ulpeflash -s 550 550.02 20.02 20.02 20.02 20.02 -adjustToSite -noSnapToGrid
#getIoFlowFlag
#
# ME1
#set llx [dbget top.fplan.coreBox_llx]
#set lly [dbget top.fplan.coreBox_lly]
#set urx [dbget top.fplan.coreBox_urx]
#set ury [dbget top.fplan.coreBox_ury]
#createRouteBlk -layer ME1 -name left_ME1_blk -box "$llx $lly [expr $llx + 0.5] $ury"
#createRouteBlk -layer ME1 -name right_ME1_blk -box "$urx $lly [expr $urx - 0.5] $ury"
#
#setSrouteMode -allowWrongWayRoute false  -treatEndcapAsCore false -extendNearestTarget false
#sroute -connect corePin -layerChangeRange {ME1(1) ME1(1)} -blockPinTarget {nearestTarget} -corePinTarget {none} -allowJogging 1 -crossoverViaLayerRange {ME1(1) ME1(1)} -nets {VDD VSS} -allowLayerChange 1 -targetViaLayerRange {ME1(1) ME1(1)} -corePinLayer ME1 -deleteExistingRoutes -detailed_log -floatingStripeTarget {followpin} -corePinWidth 0.09
#
#deleteRouteBlk -name left_ME1_blk
#deleteRouteBlk -name right_ME1_blk

# change ME1 VDD width
##deselectAll
#editSelect -net VDD -layer ME1
#editChangeWidth -width_horizontal 0.09
#deselectAll


#set llx [lindex [dbget top.fplan.coreBox] 0 0]
#set lly [lindex [dbget top.fplan.coreBox] 0 1]
#set urx [lindex [dbget top.fplan.coreBox] 0 2]
#set ury [lindex [dbget top.fplan.coreBox] 0 3]
#createRouteBlk -box "[expr $llx - 20] $lly $llx $ury" -layer {ME2 ME3 ME4 ME5 ME6} -name blk_boundary_left
#createRouteBlk -box "$urx $lly [expr $urx + 20] $ury" -layer {ME2 ME3 ME4 ME5 ME6} -name blk_boundary_right
#createRouteBlk -box "$llx [expr $lly - 20] $urx $lly" -layer {ME2 ME3 ME4 ME5 ME6} -name blk_boundary_bottom
#createRouteBlk -box "$llx $ury $urx [expr $ury + 20]" -layer {ME2 ME3 ME4 ME5 ME6} -name blk_boundary_top

# ME2
#editSelect -shape FOLLOWPIN
#editDuplicate -layer_horizontal ME2 -layer_vertical ME2
#deselectAll
#setSrouteMode -allowWrongWayRoute false  -treatEndcapAsCore false -extendNearestTarget false
#sroute -connect corePin -layerChangeRange {ME2(2) ME2(2)} -blockPinTarget {nearestTarget} -corePinTarget {none} -allowJogging 1 -crossoverViaLayerRange {ME2(2) ME2(2)} -nets {VDD VSS} -allowLayerChange 1 -targetViaLayerRange {ME2(2) ME2(2)} -corePinLayer ME2 -deleteExistingRoutes -detailed_log -floatingStripeTarget {followpin} 
#setViaGenMode -respect_stdcell_geometry true -use_trim_metal_enclosure true -optimize_cross_via true -partial_overlap_threshold 0 -ignore_DRC false
#editPowerVia -bottom_layer ME1 -top_layer ME2 -add_vias 1 -orthogonal_only 0
#setViaGenMode -reset

#foreach inst [dbget top.insts.name or_uart/organ/tissue_*] {
#		set bbox [dbget [dbget -p top.insts.name $inst].box]
#		createRouteBlk -box $bbox -layer {ME5 ME6} -name blk_$inst
#}

#####################################################################################################################################################
setAddRingMode -ring_target core_ring -extend_over_row 1 -ignore_rows 0 -avoid_short 1 -skip_crossing_trunks none -stacked_via_top_layer ME6 -stacked_via_bottom_layer ME5 -via_using_exact_crossover_size 1 -orthogonal_only true -skip_via_on_pin {  standardcell } -skip_via_on_wire_shape {  noshape }  
addRing -nets {VDD VDD  VSS VSS} -type core_rings -follow core -layer {top ME5 bottom ME5 left ME6 right ME6} -width {top 5 bottom 5 left 5 right 5} -spacing {top 3 bottom 3 left 3 right 3} -offset {top 3 bottom 3 left 3 right 3} -center 1 -extend_corner {} -threshold 0 -jog_distance 0 -snap_wire_center_to_grid None -use_interleaving_wire_group 1

##############################################################
# connect io to power ring

setSrouteMode -allowWrongWayRoute false  -treatEndcapAsCore false -extendNearestTarget true
sroute -connect padPin -layerChangeRange {ME6(6) ME5(5)} -blockPinTarget {nearestTarget} -corePinTarget {farthestPadRing} -allowJogging 1 -crossoverViaLayerRange {ME6(6) ME1(1)} -nets {VDD VSS} -allowLayerChange 1 -targetViaLayerRange {ME6(6) ME1(1)} -corePinLayer ME6 -deleteExistingRoutes -detailed_log -padPinLayerRange {ME6(6) ME1(1)} -padPinPortConnect allPort -padPinTarget ring

#setViaGenMode -reset
#setViaGenMode -partial_overlap_threshold 1
#setViaGenMode -invoke_verifyGeometry true
#setViaGenMode -ignore_DRC false
#editPowerVia -bottom_layer ME5 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net VDD 
#editPowerVia -bottom_layer ME5 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net VSS

# ME1
#editSelect -shape FOLLOWPIN
#editDuplicate -layer_horizontal ME2 -layer_vertical ME2
#deselectAll
setSrouteMode -allowWrongWayRoute false  -treatEndcapAsCore false -extendNearestTarget false
sroute -connect corePin -layerChangeRange {ME1(1) ME1(1)} -blockPinTarget {nearestTarget} -corePinTarget {none} -allowJogging 1 -crossoverViaLayerRange {ME1(1) ME1(1)} -nets {VDD VSS} -allowLayerChange 1 -targetViaLayerRange {ME1(1) ME1(1)} -corePinLayer ME1 -deleteExistingRoutes -detailed_log -floatingStripeTarget {followpin} 
#setViaGenMode -respect_stdcell_geometry true -use_trim_metal_enclosure true -optimize_cross_via true -partial_overlap_threshold 0 -ignore_DRC false
#editPowerVia -bottom_layer ME1 -top_layer ME2 -add_vias 1 -orthogonal_only 0
#setViaGenMode -reset

#ME3
#setViaGenMode -reset
#setViaGenMode -partial_overlap_threshold 1
#setViaGenMode -invoke_verifyGeometry true
#setAddStripeMode -reset
#setAddStripeMode -stacked_via_top_layer ME3 -stacked_via_bottom_layer ME2 -via_using_exact_crossover_size true -over_row_extension true
#addStripe -nets {VDD VSS} -layer ME3 -direction vertical -width 0.64 -spacing 0.21 -set_to_set_distance 18 -start_from left -start 6
#addStripe -nets {VDD VSS} -layer ME3 -direction horizontal -width 1 -spacing 0.5 -set_to_set_distance 36 -start_from bottom -start 115

#ME4
setViaGenMode -reset
setViaGenMode -partial_overlap_threshold 1
setViaGenMode -invoke_verifyGeometry true
setAddStripeMode -reset
setAddStripeMode -stacked_via_top_layer ME4 -stacked_via_bottom_layer ME1 -via_using_exact_crossover_size true -over_row_extension true  
#addStripe -nets {VDD VSS} -layer ME4 -direction horizontal -width 0.64 -spacing 0.21 -set_to_set_distance 18 -start_from left -start 6
addStripe -extend_to design_boundary -nets {VDD VSS} -layer ME4 -direction vertical -width 1 -spacing 4 -set_to_set_distance 10 -start_from left -start 115


# ME5
setViaGenMode -reset
setViaGenMode -partial_overlap_threshold 1
setViaGenMode -invoke_verifyGeometry true
setAddStripeMode -reset
setAddStripeMode -stacked_via_top_layer ME5 -stacked_via_bottom_layer ME4 -via_using_exact_crossover_size true -over_row_extension true -skip_via_on_pin {}

#addStripe -nets {VDD VSS} -layer ME5 -direction vertical -width 0.64 -spacing 0.21 -set_to_set_distance 6 -start_from left -start 5
addStripe -extend_to design_boundary -nets {VDD VSS} -layer ME5 -direction horizontal -width 4 -spacing 1 -set_to_set_distance 30 -start_from bottom -start 115
editPowerVia -bottom_layer ME4 -top_layer ME5 -add_vias 1 -orthogonal_only 0 -net {VDD VSS} 
editPowerVia -bottom_layer ME5 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net {VDD VSS}

# ME6
setViaGenMode -reset
setViaGenMode -partial_overlap_threshold 1
setViaGenMode -invoke_verifyGeometry true
setAddStripeMode -reset
setAddStripeMode -stacked_via_top_layer ME6 -stacked_via_bottom_layer ME5
#addStripe -nets {VDD VSS} -layer ME6 -direction horizontal -width 1.5 -spacing 0.5 -set_to_set_distance 10 -start_from bottom -start 5 -extend_to design_boundary
addStripe -nets {VDD VSS} -layer ME6 -direction vertical -width 6 -spacing 2.3 -set_to_set_distance 16.6 -start_from left -start 115 -extend_to design_boundary
####################################################################################################################################################
#manual stretch
return
set box [lindex [dbget [dbget -p top.insts.name ESD_clamp_core_power2ground].box] 0]
setViaGenMode -ignore_DRC true
editPowerVia -bottom_layer ME4 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net {VDD VSS} -area $box
#deleteAllPowerPreroutes 

#foreach inst [dbget top.insts.name or_uart/organ/tissue_*] {
#		foreach net [dbget [dbget -p top.insts.name $inst].pgInstTerms.net.name] {
#				set rect [dbget [dbget -p2 [dbget -p2 [dbget -p top.insts.name $inst].pgInstTerms.net.name $net].term.pins.layerShapeShapes.layer.name ME6].shapes.rect]
#				set bbox [dbTransform -inst $inst -localPt $rect]
#				foreach box $bbox {
#						set llx [lindex $box 0]
#						set lly [lindex $box 1]
#						set urx [lindex $box 2]
#						set ury [lindex $box 3]
#						set new_llx [expr $llx - 69]
#						set new_urx [expr $urx + 69]
#						add_shape -layer ME6 -shape STRIPE -rect "$new_llx $lly $new_urx $ury" -status FIXED -net $net
#				}
#		}
#}
#
#foreach inst [dbget top.insts.name or_uart/organ/tissue_*] {
#		set bbox [dbget [dbget -p top.insts.name $inst].box]
#		set llx [lindex $bbox 0 0]
#		set lly [lindex $bbox 0 1]
#		set urx [lindex $bbox 0 2]
#		set ury [lindex $bbox 0 3]
#		set new_llx [expr $llx - 69]
#		set new_urx [expr $urx + 69]
#		createRouteBlk -box "$new_llx $lly $new_urx $ury" -layer ME6 -name blk_M6_$inst
#}

# ME5
#setViaGenMode -reset
#setViaGenMode -partial_overlap_threshold 1
#setViaGenMode -invoke_verifyGeometry true
#setAddStripeMode -reset
#setAddStripeMode -stacked_via_top_layer ME5 -stacked_via_bottom_layer ME2 -via_using_exact_crossover_size true -over_row_extension true


## ME6
#setViaGenMode -reset
#setViaGenMode -partial_overlap_threshold 1
#setViaGenMode -invoke_verifyGeometry true
#setAddStripeMode -reset
#setAddStripeMode -stacked_via_top_layer ME6 -stacked_via_bottom_layer ME4
#addStripe -nets {VDD VSS} -layer ME6 -direction horizontal -width 1.5 -spacing 0.5 -set_to_set_distance 12 -start_from bottom -start 5 -extend_to design_boundary
#
#deleteRouteBlk -name blk_M6_*
#
#editPowerVia -bottom_layer ME5 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net VDD 
#editPowerVia -bottom_layer ME5 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net VSS

#deleteRouteBlk -name blk_boundary_*

###
# power ring
#setAddRingMode -ring_target core_ring -extend_over_row 1 -ignore_rows 0 -avoid_short 1 -skip_crossing_trunks none -stacked_via_top_layer ME7 -stacked_via_bottom_layer ME6 -via_using_exact_crossover_size 1 -orthogonal_only true -skip_via_on_pin {  standardcell } -skip_via_on_wire_shape {  noshape }  

## ME7
#setViaGenMode -reset
#setViaGenMode -partial_overlap_threshold 1
#setViaGenMode -invoke_verifyGeometry true
#setAddStripeMode -reset
#setAddStripeMode -stacked_via_top_layer ME7 -stacked_via_bottom_layer ME6
#addStripe -nets {VDD VSS} -layer ME7 -direction vertical -width 4 -spacing 1.0 -set_to_set_distance 10 -start_from bottom -start 110 -extend_to design_boundary

##########################
############################################################################
##########################################################################################################################################
# connect io to power ring
#deleteRouteBlk -name VDDIO_ME7_blk*
#deleteRouteBlk -name VSSIO_ME7_blk*

#setSrouteMode -allowWrongWayRoute false  -treatEndcapAsCore false -extendNearestTarget true
#sroute -connect {padPin} -layerChangeRange {ME6(6) ME1(1)} -blockPinTarget {nearestTarget} -corePinTarget {farthestPadRing} -allowJogging 1 -crossoverViaLayerRange {ME6(6) ME1(1)} -nets {VDD VSS} -allowLayerChange 1 -targetViaLayerRange {ME6(6) ME1(1)} -corePinLayer ME6 -deleteExistingRoutes -detailed_log -padPinLayerRange {ME6(6) ME1(1)} -padPinPortConnect allPort -padPinTarget ring

#sroute -connect {padPin} -layerChangeRange {ME6(6) ME5(6)} -blockPinTarget {nearestTarget} -corePinTarget {farthestPadRing} -allowJogging 1 -crossoverViaLayerRange {ME6(6) ME5(6)} -nets {VDD VSS} -allowLayerChange 1 -targetViaLayerRange {ME6(6) ME5(6)} -corePinLayer ME6 -deleteExistingRoutes -detailed_log -padPinLayerRange {ME6(6) ME5(5)} -padPinPortConnect allPort -padPinTarget ring

#sroute -blockPinTarget {nearestTarget} -corePinTarget {farthestPadRing} -allowJogging 1 -crossoverViaLayerRange {ME6(6) ME1(1)} -nets {VDD VSS} -allowLayerChange 1 -deleteExistingRoutes -detailed_log -padPinPortConnect allPort -padPinTarget ring

#setViaGenMode -reset
#setViaGenMode -partial_overlap_threshold 1
#setViaGenMode -invoke_verifyGeometry true
#setViaGenMode -ignore_DRC false
#editPowerVia -bottom_layer ME1 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net VDD 
#editPowerVia -bottom_layer ME1 -top_layer ME6 -add_vias 1 -orthogonal_only 0 -net VSS

